The architecture: digital in-memory compute
In a conventional accelerator, weights live in memory and are fetched to compute units for every operation. During decode, when a model generates one token at a time, that fetch dominates: the arithmetic per weight is tiny, so the processor spends most of its time waiting on memory and most of its energy on moving bytes rather than computing with them.
In-memory compute inverts this by performing the multiply-accumulate operations within or immediately adjacent to the memory arrays holding the weights. The data does not travel; the computation goes to it.
The word digital in d-Matrix's approach is the important qualifier. Analog in-memory compute has been researched for years and offers extraordinary theoretical efficiency, but it introduces noise, drift, calibration burden and precision limits that make production deployment difficult. d-Matrix implements the same locality principle in the digital domain, accepting a lower theoretical ceiling in exchange for deterministic, reproducible numerical behaviour — the kind of engineering trade-off that separates research demonstrations from shipping products.